The present invention relates generally to frequency synthesizers, and more particularly, to a low noise, fine frequency step synthesizer.
In prior art systems, the phase locked synthesized frequency provided by a frequency synthesizer either has many fine steps with high phase noise or has low phase noise with very limited tuning step size. No conventional technology provides both low phase noise and synthesized frequencies having many fine steps at the same time. More specifically, the patents listed below disclose conventional synthesizers that cannot provide both low phase noise and synthesized frequencies having many fine steps at the same time.
The prior art patents referred to above are identified as follows: U.S. Pat. No. 4,940,950 entitled "Frequency Synthesis Method and Apparatus Using Approximation to Provide Closely Spaced Discret Frequencies Over a Wide Range with Rapid Acquisition," issued to Helfrick, U.S. Pat. No. 4,965,533 entitled "Direct Digital Synthesizer Driven Phase Lock Loop Frequency Synthesizer," issued to Gilmore, U.S. Pat. No. 4,912,433 entitled "VCO Controlled by Separate Phase Locked Loop," issued to Motegi et al., U.S. Pat. No. 4,234,929 entitled "Control Device for a Phase Lock Loop Vernier Frequency Synthesizer," issued to Riley, Jr., U.S. Pat. No. 4,388,597 entitled "Frequency Synthesizer Having Plural Phase Locked Loops," issued to Bickley et al., and U.S. Pat. No. 4,912,432 entitled "Plural Feedback Loop Digital Frequency Synthesizer," issued to Galani et al. Of these references, the Bickley et al. and Galani et al. patents disclose plural phase locked loop synthesizers, and are considered pertinent to the present invention.
The Bickley et al. patent employs three phase locked loops to achieve synthesis. The synthesizer includes a first phase locked loop comprising a mixer and a phase detector. A second phase locked loop having a programmable divider supplies a reference frequency in predetermined steps to the mixer, while a third phase locked loop provides a reference frequency in predetermined steps to the phase detector, which steps are different from the steps provided by the second phase locked loop. Also, in a preferred embodiment, a fourth phase locked loop provides a reference signal to a mixer in the third phase locked loop to reduce the operating frequency therein and the output of the fourth phase locked loop is mixed with an output from the first phase locked loop to extend the range of the synthesizer.
The Galani et al. patent discloses an indirect digital frequency synthesizer adapted to produce a signal having a selected one of a plurality of relatively closely spaced frequencies and having a relatively fast frequency switching time. Multiple feedback loops are fed by reference frequency signals whose frequency is greater than the desired frequency separation provided by the synthesizer. The bandwidth of each of the feedback loops is less than the frequency of the reference frequency fed to each loop, and achievement of frequency separation less than the frequency of either of the reference frequencies enables each of the feedback loops to have increased bandwidth and therefore reduced frequency switching times and increased noise suppression.